Prof. Dr. Taehyou Oh | Analog | Best Researcher Award

Professor | Kwangwoon University | South Korea

Prof. Dr. Taehyou Oh is an accomplished scholar in high-speed integrated circuit design with distinguished expertise in advanced I/O architectures, equalization techniques, and multi-channel communication systems. His research centers on high-performance high-speed I/O circuits, including MIMO-based equalization, crosstalk cancellation, far-end crosstalk suppression, adaptive calibration algorithms, and low-power high-data-rate transceiver architectures for next-generation memory and chip-to-chip interfaces. He has made influential contributions to the development of multichannel I/O systems, including innovative analog-IIR receiver designs, FIR transmit drivers, quadrature DFE verification frameworks, and architectures employing signal reutilization for enhanced bandwidth efficiency. His work integrates deep theoretical modeling, algorithm development, mixed-signal circuit implementation, and prototype validation in advanced CMOS technologies. Prof. Oh has authored widely cited journal articles in leading venues such as the IEEE Journal of Solid-State Circuits and has delivered multiple award-winning conference papers presenting breakthroughs in MIMO equalization and high-speed I/O performance optimization. He is also the author of a specialized monograph on multi-channel high-speed I/O circuits published by an international scientific press. His professional experience spans academic research laboratories and global semiconductor companies, where he contributed to channel modeling, timing analysis, and high-speed link verification for advanced computing systems. His technical skill set includes analog and mixed-signal IC design, behavioral modeling, high-frequency simulation, algorithmic prototyping, and expertise with industry-standard tools such as Cadence, ADS, and MATLAB. Prof. Oh’s work continues to shape the evolution of high-speed interface technologies and next-generation communication solutions.

Profile: Scopus | Orcid | Google Scholar

Featured Publications

Oh, T., & Harjani, R. (2013). A 12-Gb/s multichannel I/O using MIMO crosstalk cancellation and signal reutilization in 65-nm CMOS. IEEE Journal of Solid-State Circuits, 48(6), 1383–1397.

Oh, T., & Harjani, R. (2011). A 6-Gb/s MIMO crosstalk cancellation scheme for high-speed I/Os. IEEE Journal of Solid-State Circuits, 46(8), 1843–1856.

Oh, T., & Harjani, R. (2010). A 5 Gb/s 2×2 MIMO crosstalk cancellation scheme for high-speed I/Os. In Proceedings of the IEEE Custom Integrated Circuits Conference (pp. 1–4).

Oh, T., Ward, D., & Dutton, R. (1980). IEEE JSSC (SC-15, 636–643). IEEE Journal of Solid-State Circuits.

Oh, T., & Harjani, R. (2015). Adaptive techniques for joint optimization of XTC and DFE loop gain in high-speed I/O. ETRI Journal, 37(5), 906–916.